The present invention relates to a semiconductor device and a method of producing the semiconductor device.
A bipolar transistor is capable of running at a high speed as compared with a MOSFET, and has a high current drive performance. Therefore, the bipolar transistor is suitable for an LSI for driving a laser for light transmission or a power amplifier of a cellular phone. When the bipolar transistors are mounted in a single chip together with MOSFETs capable of high density mounting, it is possible to obtain performance difficult to achieve in an LSI formed only of MOSFETs.
A conventional process of producing a BiCMOS formed of bipolar transistors and CMOSs, i.e., p-type MSFETs and n-type MOSFETs, on a single chip will be explained with reference to FIGS. 7(A) to 7(C) (refer to Patent Reference 1). FIGS. 7(A) to 7(C) are views showing a conventional process of producing the BiCMOS.
A silicon oxide layer 220 is formed on a silicon substrate 210, and a single crystal silicon layer 230 is formed on the silicon oxide layer 220 to form an SOI substrate 205 (FIG. 7(A)). LOCOS layers 300 are formed in the single crystal silicon layer 230 for separating elements, so that the single crystal silicon layer 230 is divided into a single crystal silicon layer 238 in a MOSFET forming area 258 and a single crystal silicon layer 235 in a bipolar transistor forming area 255. After the LOCOS layers 300 are formed in the single crystal silicon layer 230 to form a structure shown in FIG. 7(A), an oxide layer 260 is deposited on an entire upper surface of the structure with CVD method, and the single crystal silicon layer 235 in the bipolar transistor forming area 255 is exposed (FIG. 7(B)).
A single crystal silicon layer 236 is formed on the single crystal silicon layer 235 in the bipolar transistor forming area 255 through selective epitaxial growth of silicon. After the single crystal silicon layer 236 is formed, a portion of the oxide layer 260 corresponding to the MOSFET forming area 258 is removed (FIG. 7(C)). Then, a MOSFET is formed on the single crystal silicon layer 238 in the MOSFET forming area 258, and a bipolar transistor is formed on the single crystal silicon layers 235 and 236 in the bipolar transistor forming area 255, thereby obtaining the BiCMOS.
In the method of forming the BiCMOS on the SOI substrate described above, a LOCOS layer for electrically separating the bipolar transistor tends to be shrunk during a heating process for forming elements such as MOSFET, thereby generating stress in an active area. In order to solve this problem, Patent Reference 2 has proposed a method of forming a BiCMOS using a substrate having a double SOI structure.    Patent Reference 1: Japanese Patent Publication (Kokai) No. 06-69430    Patent Reference 2: Japanese Patent Publication (Kokai) No. 2001-274234
In the manufacturing method using the substrate having the double SOI structure, it is possible to reduce stress in the active area, thereby obtaining a stable BiCMOS. However, when a vertical type bipolar transistor with high performance and high mounting density is produced, it is still difficult to reduce a collector resistance at a bottom portion thereof.
In view of the problems described above, an object of the present invention is to provide a method of producing a semiconductor device, in which it is possible to provide a low resistance layer with an appropriate shape at a bottom portion of a vertical type bipolar transistor.
Further objects and advantages of the invention will be apparent from the following description of the invention.